The present invention relates to high-speed analog/digital converters and more particularly to interpolation-type analog/digital converters.
FIG. 1 very schematically shows the general architecture of an N-bits interpolation analog/digital converter.
The input analog value V.sub.e is compared in p input comparators C.sub.1 . . . C.sub.i . . . C.sub.p to reference voltages supplied, for example, by a stepped resistor bridge r.sub.i. The output voltages s.sub.i of comparators C.sub.i are combined into r groups: the output s.sub.i of comparator C.sub.i with outputs s.sub.i-r, s.sub.i-2r . . . and s.sub.i+r, s.sub.i+2r . . . and, similarly, the output s.sub.i+1 of comparator C.sub.i+1 with outputs s.sub.i+1+r, s.sub.i+1+2r, . . . , and s.sub.i+1-r, s.sub.i+1 2r . . . , etc., for providing the combined outputs S.sub.1 . . . S.sub.r. Each of the r combined outputs S.sub.1 . . . S.sub.r results from folding as will be explained in relation with FIG. 2, and is then applied to r interpolation circuits I.sub.1 . . . I.sub.r, each of which achieves interpolation in q+1 voltage sub intervals, each of which corresponds to the division by q+1 of the interval between the reference voltages applied to two successive comparators C.sub.i. The outputs s.sub.i of comparators C.sub.i and the interpolator outputs I.sub.1 -I.sub.r are applied to a storage and coding circuit 10 to supply to the output conductors a digital value corresponding to the amplitude of the input analog signal. Such a converter is for example described in "An 8-bit 50 MHz Video ADC with folding and interpolation techniques", R. Van de Grift et al, pages 94-95, ISSCC 87.
With p input comparators and q interpolations, an N-bits analog/digital converter is achieved such that 2.sup.N =p(q+1) by reducing the total number of comparators which, instead of being equal to 2.sup.N, is equal to p(input comparators)+r(q+1) (interpolation comparators). Since r is generally relatively low, this leads, as soon as the bit number, N, of the analog/digital converter goes high, for example higher than 8, to substantially reduce the number of input comparators, this reduction in the number of input comparators being well over the number of the additional comparators required in the r interpolation circuits.
FIG. 2 shows a conventional exemplary implementation and combination of successive comparators of a same group among the r groups of comparators. It is assumed that r is equal to 4 and FIG. 2 shows the successive comparators C.sub.1, C.sub.5, C.sub.9, C.sub.13 . . . . Each comparator comprises in the given example two NPN transistors, the emitters of which are interconnected and connected to the ground through a current source I.sub.1. The base of the first transistor receives input voltage and the base of the second transistor receives the reference voltage corresponding to this comparator. The collector of the first transistor (T.sub.11, T.sub.51, T.sub.91, T.sub.131), of each comparator is connected to a high supply terminal through a resistor R and the signal on this collector is copied by an NPN transistor (T.sub.1, T.sub.5, T.sub.9, T.sub.13 . . . ), the collector of which is connected to a high voltage source and the emitter forms the output terminal S.sub.1. In fact, FIG. 2 shows two output lines S.sub.1a and S.sub.1b grounded through current sources I.sub.2, each of which is connected to every two transistors, so that quasi-complementary signals are obtained on lines S.sub.1a and S.sub.1b. The collector of the second transistor (T.sub.12, T.sub.52, T.sub.92, T.sub.132) of each comparator is connected to the collector of the first transistor of the next comparator. Thus, the collector of the second transistor T.sub.12 of comparator C.sub.1 is connected to the collector of the first transistor T.sub.51 of comparator C.sub.5 . . . .
FIG. 3 shows the evolution of signal S.sub.1a as a function of the input voltage V.sub.e.
When V.sub.e is lower than V.sub.1, transistors T.sub.11, T.sub.51, T.sub.91, T.sub.131 are off while transistors T.sub.12, T.sub.52, T.sub.92, T.sub.132 are on. Transistor T.sub.11 being off, transistor T.sub.1 has its base set to "1", causing line S.sub.1a to go high. On the contrary, transistors T.sub.5, T.sub.13, . . . , the bases of which are at a low level because of the conductive state of transistors T.sub.12, T.sub.52, T.sub.92 . . . impose a low level on line S.sub.1b.
When voltage V.sub.e ranges from V.sub.1 to V.sub.5, transistor T.sub.11 is on. Therefore, the base of transistor T.sub.1 is at a low level. Transistors T.sub.12 and T.sub.51 are slightly conductive, then the base of transistor T.sub.5 is therefore at a high level and line S.sub.1b goes high and the bases of transistors T.sub.52, T.sub.92, T.sub.132 . . . , remain at a low level. Thus, except for the base of transistor T.sub.5, all the bases of transistors T.sub.1, T.sub.9, T.sub.13 . . . are at a low level and line S.sub.1a is at a low level. Then, the voltage on line S.sub.1a alternatively goes at a low and high level as the voltage V.sub.e increases. The signal changes its state close to each voltage V.sub.1, V.sub.5, V.sub.9, V.sub.13 . . . . Interpolation is achieved in this area.
The interpolation will be preferably achieved by using signal S.sub.1a and its quasi-complementary signal S.sub.1b.
Still assuming that r is equal to 4, that is, four outputs S.sub.1, S.sub.2, S.sub.3 and S.sub.4 of the input comparators are applied to the interpolation circuits I.sub.1 . . . I.sub.4, FIG. 4A shows the shape of outputs S.sub.1 -S.sub.4 and more particularly outputs S.sub.1a -S.sub.4a and FIG. 4B shows the shape of curves S.sub.1a and S.sub.2a close to voltages V.sub.1 and V.sub.2. The interpolations are achieved close to these changes of state in interpolators I.sub.1 . . . I.sub.r. However, the differential stage used, as shown in FIG. 2, is highly non linear. As a result, on the one hand, voltages V.sub.1 and V.sub.2 must not be too different and, on the other, it is not possible to increase the number of interpolation points, 4 seeming to be a maximum.
But, it appears that, if it is desired to decrease the number of comparators, and therefore the surface and consumption of an analog/digital converter, it would be suitable, when the number of bits that is desired to obtain is high, for example equal to 10, to increase the number of interpolation levels of each interpolator.